library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;



entity pc is
	generic (Tpd : Time := unit_delay);
	port (
		clock : in bit;
		clear : in bit;
		load : in bit;
		inc : in bit;
		d : in bit_6;
		q : out bit_6
	);
end pc;


architecture pc_arh of pc is
begin
	process(clear, load, inc, d)
	variable data: integer range 0 to 2**6 - 1;
	begin
		if clock'event and clock = '1' then
			if clear = '1' then data := 0;
			elsif load = '1' then data := to_integer(d);
			elsif inc = '1' then data := data + 1;
			end if;
		end if;
		q<= to_bits(data,6) after Tpd;
	end process;
end pc_arh;